Publications

2024

1. OOPSLA

   UniSparse: An Intermediate Language for General Sparse Format Customization

   Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, and Zhiru Zhang

   Proceedings of the ACM on Programming Languages, OOPSLA, 2024

   PDF Code DOI

2023

1. IEEE CAL

   An Intermediate Language for General Sparse Format Customization

   Jie Liu, Zhongyuan Zhao, Zijian Ding, Benjamin Brock, Hongbo Rong, and Zhiru Zhang

   IEEE Computer Architecture Letters, 2023

   PDF Code DOI

2021

1. IEEE

   An IMU-Based Real-Time Measuring System for Acetabular Prosthesis Implant Angles in THR Surgeries

   Hong Chen, Zhecheng Yang, Jilin Zhang, Jie Liu, Hao Tang, Yixin Zhou, Binjie Zhu, and Zhihua Wang

   IEEE Sensors Journal, 2021

   DOI

2020

1. MICRO

   Matraptor: A sparse-sparse matrix multiplication accelerator based on row-wise product

   Nitish Srivastava, Hanchen Jin, Jie Liu, David Albonesi, and Zhiru Zhang

   In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020

   PDF DOI

2019

1. FPGA poster

   Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis

   Jie Liu, and Jason Cong

   In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, 2019

   Abs Code DOI

   Matrix decomposition is a fundamental topic in numerical algebra, with its applications frequently seen in a wide range of engineering fields. Many specific systolic array structures of matrix decomposition algorithms have been proposed previously to maintain high performance as the problem size scales up. In this paper, we broadly explore different mappings of most frequently used Cholesky, LU and QR decomposition algorithms to systolic arrays. We follow the canonical mapping method to define the systolic array design space. By selecting different linear projection vectors on the dependency graph of each algorithm, multiple one-dimensional and two-dimensional systolic arrays are generated. To obtain better performance, we also introduce streaming dataflow on the top module which enables heterogeneous PEs to work in data-driven manners. All designs are implemented using the Xilinx Vivado High-Level Synthesis tools. We show in our experimental results the differences in performance and resource consumption of each mapping. We also demonstrate up to 50.13x and 4.58x better throughput of our implementations compared with the Xilinx HLS linear algebra library and the LAPACK library on CPUs.

2018

1. IEEE

   Measurement System for Attitude of Anterior Pelvic Plane and Implantation of Prothesis in THR Surgery

   Hong Chen, Zhe Cao, Shaojie Su, Jie Liu, and Zhihua Wang

   IEEE Transactions on Instrumentation and Measurement, 2018

   DOI